This invention relates to a dual bus memory controller.
A computer system with multiple processors relies on memory to store data and instructions processed and executed by the processors. The processors access the memory by generating memory access requests which are converted by a memory controller into memory access commands that are compatible with the memory. The rate at which the memory controller can process memory access requests may be slower than the rate at which the memory can process the commands. Consequently, the memory controller can adversely affect the rate at which data is exchanged between the memory and the processors.